1. Field of the Invention
The present invention relates to scan flip-flops and, more particularly, to a scan flip-flop that simultaneously holds a logic value shifted into the flop from a serial load, and a logic value loaded into the flop from a subsequent parallel load.
2. Description of the Related Art
The fundamental approach to testing digital logic at the end of a manufacturing line is to apply a series of logic patterns to the input pins, and then evaluate the logic patterns on the output pins to insure that the proper values are present. The series of logic patterns, in turn, are selected so that every path through the logic is exercised.
While simple in concept, the complexity of this approach increases exponentially as the depth of the logic, i.e., the number of gates between the input and output pins, increases. With deep logic, it is often the case that some portion of the logic can not be exercised by simply applying different patterns to the input pins.
One common technique for limiting the depth of the logic is to use a partitioned logic circuit. With a partitioned logic circuit, special test flip-flops, known as scan flip-flops or scan flops, are chained together at regular intervals to divide the logic circuit into a plurality of logic subcircuits.
FIG. 1 shows a block diagram that illustrates a conventional partitioned logic circuit 100. As shown in FIG. 1, logic circuit 100 includes a series of logic subcircuits SC1-SCm, and a series of scan flop chains FC1-FCn which connect the subcircuits SC1-SCm together.
As further shown in FIG. 1, the first logic subcircuit SC1 is connected to a plurality of input pins 102, while the last logic subcircuit SCm is connected to a plurality of output pins 104. Each scan flop chain FC, in turn, is positioned between an adjacent pair of subcircuits SC so that each subcircuit SC, except for the first, has a corresponding input chain, and each subcircuit SC, except for the last, has a corresponding output chain.
For example, flop chain FC1 functions as the output chain for subcircuit SC1, and the input chain for subcircuit SC2, while flop chain FC2 functions as the output chain for subcircuit SC2, and the input chain for subcircuit SC3. (Flop chains are typically not required to input test patterns into the first subcircuit, or to output patterns from the last subcircuit as these functions are provided by the testing equipment).
In addition, each scan flop chain FC includes a plurality of scan flops 110 which each have a parallel input 112, a parallel output 114, a serial input 116, and a serial output 118. As shown, the outputs from a subcircuit SC are connected to the parallel inputs 112 of the flops 110 in the corresponding output chain, while the inputs to a subcircuit SC are connected to the parallel outputs 114 of the flops 110 in the corresponding input chain. Further, the serial inputs and outputs 116 and 118 are utilized to serially connect the flops 110 in a flop chain FC.
FIGS. 2A-2D show block diagrams that illustrate the operation of partitioned logic circuit 100. FIGS. 2A-2D are similar to FIG. 1 and, as a result, utilize the same reference numerals to designate the common structures. FIG. 3 shows a timing diagram that further illustrates the operation of circuit 100.
In operation, logic circuit 100 functions in a logic mode and a test mode. When in the logic mode, logic signals are clocked through the scan flops 110 in a manner which allows logic circuit 100 to function as a single logic device.
Prior to entering the test mode, a series of test patterns is selected for each subcircuit SC so that, when the test patterns are applied to the subcircuits SC, all of the logic paths through the subcircuits SC are exercised. For example, as shown in FIG. 2A, test patterns FP1-FPr, SP1-SPr, TP1-TPr, and LP1-LPr have been selected for subcircuits SC1, SC2, SC3, and SCm, respectively.
When in the test mode, the first test pattern FP1 is presented to the parallel inputs of the first subcircuit SC1, while the first test patterns SP1, TP1, and LP1 are serially loaded into flop chains FC1, FC2, and FCn, respectively.
For example, as shown in FIG. 2B, first test pattern [1-0-0- . . . -0] is presented to subcircuit SC1, while first test patterns [0-1-0- . . . -1], [0-0-0- . . . -1], and [1-0-0- . . . -1] are serially loaded into flop chains FC1, FC2, and FCn, respectively.
The last logic values of the first test patterns are serially loaded into the flop chains FC on the rising edge of clock cycle A as shown in FIG. 3. After this, during clock cycle A, each first test pattern propagates through the corresponding subcircuit SC, and causes a first new logic pattern to be presented to the corresponding output chains and the output pins 104.
For example, as further shown in FIG. 2B, first test pattern [1-0-0- . . . -0] , which was presented to subcircuit SC1, causes a first new logic pattern [1-1-0- . . . -0] to be presented to flop chain FC1, while first test pattern [0-1-0- . . . -1], which was loaded into flop chain FC1, causes a first new logic pattern [1-1-1- . . . -0] to be presented to flop chain FC2.
Similarly, first test pattern [0-0-0- . . . -1], which was loaded into flop chain FC2, causes a first new logic pattern [0-1-0- . . . -1] to be output from subcircuit SC3, while first test pattern [1-0-0- . . . -1] , which was loaded into flop chain FCn, causes a first new logic pattern [0-0-1- . . . -0] to be output from subcircuit SCm.
Following this, on the rising edge of clock cycle B, which is known as the parallel load cycle, flop chains FC1-FCn latch the first new logic patterns output from subcircuits SC1-SCm via the parallel inputs 112.
For example, as shown in FIG. 2C, the first new logic pattern [1-1-0- . . . -0] output from subcircuit SC1 is latched by flop chain FC1. Similarly, the first new logic pattern [1-1-1- . . . -0] output from subcircuit SC2 is latched by flop chain FC2, and the first new logic pattern [0-1-0- . . . -1] output from subcircuit SC3 is latched by flop chain FCn (assuming only four subcircuits).
Once latched, these first new logic patterns also propagate through the following logic subcircuits SC, and cause a second new logic pattern to be presented to the parallel inputs 112 of the flop chains FC1-FCn, and output on the output pins 104.
For example, as shown in FIG. 2C, the first new logic pattern [1-1-0- . . . -0] that was latched by flop chain FC1 now causes a second new logic pattern [1-0-1- . . . -0] to be presented to the parallel inputs of flop chain FC2.
Similarly, the first new logic pattern [1-1-1- . . . -0] latched by flop chain FC2 causes a second new logic pattern [0-0-0- . . . -1] to be output from subcircuit SC3, while the first new logic pattern [0-1-0- . . . -1] latched by subcircuit SCm causes a second new logic pattern [0-0-0- . . . -0] to be output to pins 104. (Note that the logic pattern presented at the parallel inputs to flop chain FC1 does not change because the test pattern FP1 has not yet changed).
Next, at time t.sub.3 in clock cycle B, the test equipment latches the second new logic pattern output from subcircuit SCm, (e.g., logic pattern [0-0-0- . . . -0]). After this, on the rising edge of clock cycle C, the second test pattern FP2 is presented to the first subcircuit SC1, while the first values of the second test patterns SP2, TP2, and LP2 are serially loaded into flop chains FC1, FC2, and FCn, respectively.
The serial load process continues until second test patterns SP2, TP2, and LP2 are serially loaded into flop chains FC1, FC2, and FCn, respectively. Thus, as shown in FIG. 2D, second test pattern [1-0-1- . . . -1] is presented to subcircuit SC1, while second test patterns [0-0-1- . . . -1] , and [0-1-0- . . . -0] are serially loaded into flop chains FC1, FC2, and FCn, respectively.
As each second test pattern is loaded into a flop chain FC, the first new logic patterns which were just latched by the flop chains FC are serially output. Thus, as shown in FIG. 2D, the first new logic pattern [1-1-0- . . . -0] output from subcircuit SC1 is output by flop chain FC1, the first new logic pattern [1-1-1- . . . -0] output from subcircuit SC2 is output by flop chain FC2, and the first new logic pattern [0-1-0- . . . -1] output from subcircuit SC3 is output by flop chain FCn (assuming only four subcircuits).
The first new logic patterns output from the flop chains FC, and the second new logic pattern read from output pins 104 are then compared to the predicted values to determine if the subcircuits SC are functioning correctly.
FIG. 4 shows a block diagram that illustrates a portion of a conventional scan flop chain 400. As shown in FIG. 4, scan flop chain 400 utilizes three scan flops 110 which include a first flop 410, a second flop 412 which is connected to first flop 410, and a third flop 414 which is connected to second flop 412.
Each scan flop 110/410, 110/412, and 110/414, in turn, includes a D-Q flip-flop 420 which has a D-input, a clock input CLK, and a Q-output; and a two-to-one multiplexor 430 which has a parallel input 112, a serial input 116, a select input that receives a test enable signal EN, and a mux output connected to the D input of flop 420.
As further shown in FIG. 4, scan flops 110/410, 110/412, and 110/414 are chained together by simply connecting the Q-output of one scan flop 110 to the serial input of the next scan flop 110 in the chain, and by connecting each of the mux select inputs.
In addition, FIG. 4 also shows that the first and second scan flops 410 arid 412 receive signals from the left-side of the drawing, and output signals to the right-side of the drawing, while the third scan flop 414 receives signals from the right-side of the drawing, and outputs signals to the left-side of the drawing.
When in the test mode, a test pattern is serially shifted into the chain by setting the test enable signal EN to a logic state that selects the serial inputs of the flops in the chain. Thus, since the outputs of each flop 110 (except the last) is connected to the serial input of the next flop 110, patterns are serially loaded by simply clocking the values into the chain.
One problem with scan testing is that, when bidirectional and switchable high-impedance I/O circuits are used, the input and output states of the pins associated with these circuits can not be determined ahead of time.
The reason the input and output states of the pins can not be determined ahead of time is that a flop, such as flop 412 of circuit 400, is used to control the input and output states of the pins, and the value which is loaded into the flop during the serial load (which sets the input or output state of the pin) may be changed by the value that is loaded into the flop during the parallel load (the rising edge of clock cycle B in FIG. 3).
Conventionally, the tester must place test patterns on the input pins prior to the rising edge of clock cycle B in FIG. 3. If on the rising edge of clock cycle B a pin changes from an input to an output pin, the test equipment will drive a value onto the pin when a value should be read from the pin. This, in turn, leads to a testing failure.
FIG. 5 shows a block diagram that illustrates a portion of a conventional partitioned logic circuit 500. FIG. 5 is similar to FIG. 4 and, as a result, utilizes the same reference numerals to designate the common structures. As shown in FIG. 5, circuit 500 includes scan flop chain 400 of FIG. 4, and a bi-directional circuit 510 which functions as a logic subcircuit, such as subcircuit SCm of FIG. 1.
As further shown in FIG. 5, bi-directional circuit 510 includes an output driver 512 which has an input connected to the Q output of scan flop 410, and an output connected to a bi-directional pin 514.
In addition, circuit 510 also includes an input driver 516 which has an input connected to bidirectional pin 514, and an output connected to the parallel input of scan flop 414. Further, an inverter 518 has an output connected to a control input of output driver 512, and an input connected to a control input of input driver 516 and the Q output of scan flop 412.
FIGS. 6A-6B show block diagrams that illustrate the operation of circuit 500. FIGS. 6A-6B are similar to FIG. 5 and, as a result, utilize the same reference numerals to designate the common structures. FIGS. 7A-7C show timing diagrams that further illustrate the operation of circuit 500.
In operation, as shown in FIGS. 6A and 7A-7C, during the serial loading of a first test pattern [1-1-1] into flop chain 400, a test enable signal EN, which is applied to the mux select inputs, is set to a logic high to select the serial inputs.
The last value of the first test pattern [1-1-1] is then shifted into flop chain 400 on the rising edge of clock cycle A. (Note in FIG. 6A that logic highs are output from flops 410, 412, and 414). The logic one output by second flop 412 turns on output driver 512 and turns off input driver 516.
Thus, based on a logic one being shifted into flop 412, the test equipment expects bi-directional pin 514 to be an output pin.
In addition, as a result of a first test pattern being shifted into the flop chain that precedes flop chain 400, a new logic pattern [1-0] is presented to the parallel inputs of flops 410 and 412. Since the test equipment expects bi-directional pin 514 to be an output pin, the logic value presented to the parallel input of flop 414 is a don't care.
Following this, at time t.sub.1 in clock cycle A, the test enable signal EN falls to a logic low which selects the parallel inputs of multiplexors 430. Next, on the rising edge of clock cycle B, flop chain 400 latches the new logic pattern [1-0].
As shown in FIGS. 7A-7C, once the new logic pattern has been latched by flop 412, the output from flop 412 falls to a logic low at time t.sub.2. Thus, the logic low now output from scan flop 412 turns off output driver 512 and turns on input driver 516.
As a result, bi-directional pin 514 has been changed from an output pin to an input pin. This change in the direction of pin 514, however, can not be detected by the test equipment as the test equipment is only aware of the values that have been serially loaded into chain 400.
Thus, the test equipment expects the output from flop 412 to remain high (as shown by the dashed line in FIG. 7C), and to read a logic value from pin 514 at time t.sub.3 (which is the same as time t.sub.1 in FIG. 3). At the same time, however, the output from flop 412 has fallen, thereby reconfiguring pin 514 to be an input pin. This indeterminate state, in turn, causes a testing error.
Similar errors occur when a switchable high-impedance circuit, such as a TRI-STATE.TM. circuit, is used. FIG. 8 shows a block diagram that illustrates a portion of a conventional partitioned logic circuit 800. As shown in FIG. 8, circuit 800 includes a portion of scan flop chain 400 of FIG. 4, and a switchable high-impedance circuit 810 which functions as a logic subcircuit, such as subcircuit SCm of FIG. 1. As shown, FIG. 8 is similar to FIG. 4 and, as a result, utilizes the same reference numerals to designate the common structures.
As further shown in FIG. 8, circuit 800 includes a driver 812 which has an input connected to the Q output of scan flop 410, an output connected to a switchable high-impedance pin 814, and a control input connected to the Q output of scan flop 412.
In operation, the logic state output from flop 412 determines the state of pin 814 in a similar way that the logic state output from flop 412 determines the state of pin 514 in FIGS. 6A and 6B. Thus, as with bi-directional pins, if the test equipment expects the output from flop 412 to remain high at the same time that the output from flop 412 has fallen, thereby reconfiguring pin 814, a testing error will result.
Thus, there is a need for a testing arrangement that guarantees the pin directions for a whole cycle.